The present invention relates to power supplies and in particular to voltage converters employing two controlled switches, one of which operates as a synchronous rectifier. The two switches are generally controlled so that both switches are never on at the same time. A “dead time” is provided between the on-times of the two switches to prevent cross conduction across the DC voltage supply between which the two switches are connected in series.
Synchronous rectification has been widely adopted for use in low voltage output converters of various topologies: Buck, boost, fly back, and forward. By substituting a MOSFET switch for a silicon or Schottky diode, rectification losses can be dramatically reduced.
For synchronous converters, it is essential that a non-overlap period (dead time) be maintained in order to prevent excessive cross conduction of the control switch with the synchronous rectifier switch. The power loss penalty for significant overlap is extremely high compared to the additional conduction losses occurring during dead time.
Still, dead time losses are significant; especially as converter operating frequency is increased. Using the example of a synchronous buck converter with the following characteristics:                Operating frequency=1 Mhz        Input voltage=12 volts        Output voltage=1 volt        Output current=40 amperes        Synchronous switch on resistance=3 mΩ        Synchronous switch body diode VF @ 40A=0.8V        
Instantaneous power loss will be 4.8 watts with the synchronous switch FET on, but 32 watts with only the body diode conducting. At the above conditions, this translates into an additional 27 mW power loss per nanosecond of dead time. Two switching edges per cycle of 20 ns dead time each results in an additional 1.088 watts of loss in the synchronous switch, a 20% increase in losses for that component. Using a Schottky diode in parallel with the MOSFET will reduce that figure by 30%-to-40%, but at additional cost and component count.
Additionally, once the body diode of the synchronous switch conducts, it is subject to a reverse recovery period and associated charge which must be swept out of the junction. This amounts to cross conduction and causes additional losses in the control FET.
The present invention seeks to minimize the power losses associated with dead time. This is accomplished by minimizing dead time to reduce body diode conduction losses, and in some cases, by allowing FET switch cross conduction to eliminate body diode conduction altogether, thus eliminating reverse recovery associated losses.
There are a number of techniques that are known for reducing dead time. These include:
Adjustable dead time. Dead time is adjusted during the design stage so that cross conduction will be avoided under all operating conditions and over the full process variation of all components involved in achieving the dead time. Process variation of semiconductors can be significant and circuit operation may be over a wide range. Consequently, when no crossover is achieved with the worst case components at the worst case conditions, dead time with best case components and conditions is excessive. This results in excessive wasted power loss.
Adaptive dead time. Adaptive dead time is an improvement over adjustable dead time in that it can adjust on the fly as conditions change, and from unit-to-unit over component variations. Essentially it is logic control where the gate of one switch is prevented from turning on, until the gate of the other switch has been detected to turn off. Superficially, this seems to solve the problem, but in practice it does not. Finite time periods are required for logic control, and for charging and discharging gates of the power switches themselves. In actual practice this results in dead times on the order of 10 ns-to-30 ns per switching transition for a total of 20 ns-to-60 ns per cycle.
Predictive dead time. Most of the problem with adaptive dead time is the time required to switch the FETs off and on. Predictive dead time solves that deficiency by using a phase locked loop or some other loop to reduce dead time until it is near zero. This appears to provide many of the same benefits as the present invention, but the use of a control loop has attendant disadvantages. Since this methodology relies on a control loop of some sort to set dead time, there is also an associated settling time in that loop. During transient conditions, cross conduction may occur while the loop tries to settle into a new steady state. If fixed dead time is programmed into the loop to avoid cross conduction, then most of the time there will be more than minimum dead time and associated losses. In any case, the loop solution relies on some arbitrary electrical conditions rather than minimizing the losses associate with dead time. Test results indicate that this method does not result in the lowest possible power losses.
Power loss minimizing dead time (PLMDT). This technique has all the advantages of the present invention, except that it does not “remember” the best dead time settings for various operating conditions. In terms of power supply operation, this optimization takes a long time—tens of milliseconds. That means that in fast load transient environments, the PLMDT operation cannot keep up with power supply changes. Averaging techniques allow the PLMDT circuitry to find an “optimum” average value that works best across a wide range of load currents. This works very well, but still falls short of having the exact right dead time for each current. PLMDT is the subject of Applicant's co-pending patent application IR-2673, U.S. Ser. No. 11/058,969 filed Feb. 16, 2005, incorporated by reference in its entirety herein.
FIG. 4 shows a converter circuit comprising transistors Q1 and Q2 wherein PLMDT is used to set the dead time. Changes in duty factor of a PWM signal 10 are used to estimate power loss changes. A multiplier block 22 is used to modulate VIN (the supply voltage to switches Q1 and Q2) with the PWM signal, producing the signal D×VIN, which is proportional to the duty factor. This signal is passed though a low pass filter 24 creating a slow moving signal which is equal to what the output voltage would be if there were no converter losses. This signal is amplified by a factor k (k×D×VIN) and split into two paths. One path goes directly to the decision comparator 26 and the other path is through, for example, a sample and hold module 28 before being applied to the decision comparator 26. The sample and hold module 28 is used to save the previous “k×D×VIN” signal so that it can be compared to the one produced after a change in dead time.
A sample and hold module 28 is shown in FIG. 4, but the sample and hold function can be implemented in various ways, including, for example, using an “N” bit memory or other equivalent techniques. Similarly, the comparator function can be performed by a logic magnitude comparator, for example, or other equivalent techniques.
The dead time processor 20 (DTP) of FIG. 4 may be implemented with logic circuitry, a microcontroller, or a microprocessor. The DTP 20 controls the sample and hold circuit 28, sets the dead time via the dead time modulators 16 and 18, and processes the “Better” signal from the output of the decision comparator. If the new signal (This D) is smaller than the previous signal (Last D), then the new dead time is “Better” (the comparator output is high) and the DTP 20 saves this new dead time value. Otherwise the new one is discarded and the old dead time is restored. A delay is required after changing the dead time to allow the power supply feedback circuitry to settle on a new duty factor. Many factors can effect this time, but in practice a time of about 100× the switching period of the power supply seems to work well.
Though not necessary to demonstrate the principle, in practice the DTP 20 preferably averages multiple decisions over a relatively long period of time before reaching a final conclusion about a particular dead time in order to obtain reliability and prevent false dead time setting due to noise or transients. Hundreds of samples or more are desirable. This effectively averages out the effect of rapid load transients on power supply duty factor. The same averaging technique is applicable if some other means besides duty factor is used to determine power loss.
PLMDT may be implemented using digital PWM or digital signal processing (DSP) implementations, but the basic algorithm remains substantially the same.
FIG. 5 shows the basic algorithm which may be implemented with a digital signal processor, microprocessor, microcontroller, or logic state machine for implementation of PLMDT. It also substantially shows an example of the process implemented by the circuitry of FIG. 4.
With reference to FIG. 5, only the flow for the sync-off channel is shown. As described below, the sync-on channel flow is substantially the same. Starting at A, assuming that the sync-off delay has been set and the result of the previous dead time was that the power loss resulting from the last dead time showed that the last sample was better than the previous sample, that is, resulting in a lower duty cycle and thus a lower power loss, entry into the flow is via “yes” at point A. A test counter that counts to “N” is incremented at 50. The current power loss is sampled and saved at 52. The dead time is shortened or decreased by one step as indicated at 54. This means the off delay is increased, since the dead time is decreased. Whether the dead time is decreased or increased initially is arbitrary. However, since the goal is to decrease power losses and this is accomplished by decreasing dead time, dead time is preferably decreased initially. In the second part (II) of the FIG. 5 flow, dead time will be increased, and the dead time that results in the lower power loss will be implemented.
A delay is implemented to allow the power supply voltage to settle as shown at 56. The new power loss (after the dead time has been changed) is now compared with the old power loss at 58. The old power loss has been saved from the previous step 52 as shown at 58A. If the new power loss is lower (for example, as determined by duty cycle), as indicated by decision block 60, flow is to block 62 wherein the “better” counter is incremented. The “better” count keeps track of the number of times the new power loss is better than the old.
If the new power loss was not better than the old power loss at step 60, the counter is not incremented. Flow is then to decision block 66 to determine if N tests are complete. As discussed above, a plurality of tests are preferably made to obtain reliable results. If N tests are not complete, flow is via line 69. At 71, the previous dead time is reinstated and a delay is implemented at 73 to allow the power supply to settle and the test counter is again incremented at 50 and the comparison is again made with the old power loss. Once N tests have been completed, exit is to 68. The dead time will have been last implemented at step 54. N tests are made to ensure that the comparisons are reliable, to account, for example, for noise or load transients which could cause an error if only a single test were made. By making multiple tests, greater accuracy and reliability is obtained.
At step 68, a determination is made if N/2+1 of the tests were better, that is, if the “better” counter shows that more than half the tests made showed a better power loss. If so, then entry is made via flow line 70 to part II of the flow. If N/2+1 tests were not better, then the old dead time is reinstated at 74 and a delay is implemented at 75 before proceeding to step 76.
At step 76, the test counter “N” is again incremented. The current power loss is saved at 78, the dead time is increased by one step at 80, reducing the sync-off delay. At 82, a delay is implemented to allow the power supply to settle. At 84, the old power loss 84A saved at step 78 is compared with the new power loss. The old power loss is shown at 84A. At step 86, a determination is made as to whether the new power loss is lower with the increased dead time. If the new power loss is lower, the “better” counter is incremented at 88. If the new power loss is not lower or after incrementing the better counter at 88, a check is made to determine if N tests have been completed. If not, a return is made via line 93 and the test counter is incremented again at 76 and the comparison at 84 is again made. Once N tests have been completed at step 90, a check is made at 92 to determine that more of the N tests were better. If this is the case, then the flow is to the synchronous on channel flow which is substantially identical to the synchronous off channel example shown in FIG. 5. The synchronous on channel dead time delay will be processed in the same way as the synchronous off channel example shown in FIG. 5. Accordingly, in the synchronous on channel, similar flow will occur in that the old power loss will be compared with the new power loss for both a decrease and an increase in the dead time, and if the power loss is better, the new dead time will be maintained, and if not, the old dead time will be restored, substantially the way as shown in the synchronous off channel example of FIG. 5.
The PLMDT technique results in optimizing the dead time. However, results are a compromise based on average circuit conditions rather than an optimum based on exact instantaneous operating conditions. The Intelligent Dead Time (IDT) technique disclosed herein solves the “speed” problems associated with PLMDT.